Designing a CMOS synthesizer RFIC Nov 17, 2007
The two popular synthesizer architectures are an integer-N and a fractional-N phase-locked loop (PLL). If an integer-N PLL can meet the requirement, it should be used because of a relatively simpler design. (EETimes)
Mosaid sells semiconductor IP business to Synopsys for $15M Jul 17, 2007
Synopsys will buy the assets and IP associated with Mosaid's double data rate (DDR) memory controller and phase locked loop (PLL) frequency regulator product families, and will also receive an exclusive licence to certain patents and pending applications associated with Mosaid's current memory controller and PLL product lines. The deal follows the $17. (Ottawa Business Journal)
MOSAID to Sell Semiconductor IP Assets to Synopsys Jul 16, 2007
Synopsys has agreed to purchase the assets and intellectual property associated with MOSAID's Double Data Rate (DDR) memory controller and Phase Locked Loop (PLL) product families. In connection with the transaction, Synopsys will also receive an exclusive license to certain patents and pending applications associated with MOSAID's current memory controller and PLL product lines. (Canada Newswire)
Toshiba Develops 60GHz Receiver Technology Using CMOS Device Jun 18, 2007
It integrates an on-chip antenna, LNA, a mixer with a preamplifier and a phase-locked loop (PLL) synthesizer in a die that is only 1. 1mm x 2. (PhysOrg.com)
Imager peek spotlights Micron's rise Feb 16, 2007
The imager includes a low-noise signal readout chain, a 12-bit analog-to-digital converter, an internal phase-locked loop and a 12- parallel to data at up to 96 megapixels per second (Mp/s), according to the paper. Page 2. (EETimes)
IMEC rolls software radio device Feb 13, 2007
The prototype software-radio IC, subbed Scaldio, is developed in a 130-nm process, integrates two LNAs, and sports dual phase-locked loop (PLL) chains (which are needed to support FDD operation). One of the LNAs operates from to 2. (EETimes)
