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    News and Articles on Phase Locked Loop



    45-nanometer Chips For Ultra-fast WiFi  Aug 14, 2009
    IMEC presented some of the results of the 45nm CMOS research at the International Solid State Circuits Conference in San Francisco in February, unveiling a 60GHz front-end receive chain, phase-locked loop and power amplifier, among other devices. The Belgian group envisions those building blocks leading to commercial 60GHz radios by 2010 that rely solely on CMOS.. (Science Daily)

    Rambus targets DDR4 DRAMs  May 28, 2009
    FlexPhase enables high data rates by overcoming the speed limitations of the direct strobing technology used in DDR3, Dynamic Point-to-Point technology is a signaling technique aimed to boost capacity and FlexClocking reduces clocking power by eliminating the need for a phase-locked loop on the DRAM.. The first two techniques are part of the Rambus XDR memory architecture. (EETimes)

    New MEMS timing chip emerges  Apr 1, 2009
    SiTime stacked its MEMS die atop an ASIC housing its programmable phase-locked loop, which can vary output frequency of the 1- to 110-MHz oscillator within four pull ranges: +/-30, 60, 120 or 240 parts per million. Output frequency and pull ranges are programmed by SiTime 24 hours after receiving orders for samples, followed by volume shipments within two weeks. (EETimes)

    Piezoelectric MEMS said to lower power consumption  Feb 13, 2009
    But silicon resonators are less stable than quartz, forcing MEMS makers to include temperature compensation using a power-hungry phase-locked loop (PLL). By adding a piezoelectric thin-film atop its silicon resonator, and using a switched capacitor method for performing temperature compensation (instead of a PLL), the Swiss Center for Electronics (CSEM) is claiming a 1,000-fold decrease in power consumption in a paper presented this week during the International Solid-State Circuits Conference. (EETimes)

    New High Frequency Amplifier Harnesses Millimeter Waves In Silicon For Fast Wireless  Feb 13, 2009
    9, 2009) A 60GHz front-end receive chain, phase-locked loop and power amplifier in 45nm digital CMOS technology has been created. These building blocks pave the way to second-generation 60GHz radios by 2010. (Science Daily)

    Engineers push into 40G networking  Feb 12, 2009
    To create the chip, engineers had to build a 20 GHz phase-locked loop with low phase noise yet a wide range. They also had to distribute that clock with reasonable power while optimizing chip timing in the face of process and temperature variations. (EETimes)




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